Because of the large number of layers needed to produce an integrated circuit, it has become standard practice to introduce a planarizing step at regular intervals. The most widely used technique for this has been chemical mechanical polishing (CMP). CMP continues to be the etch method of choice because the etch front associated with it tends to be planar, regardless of the initial topography of the surface.
It is, however, well known that, during CMP, etching tends to proceed at a faster rate over regions that are softer than surrounding regions. This leads to a ‘dishing’ problem in which undesired concavities are obtained in a surface after it has been subjected to CMP, said concavities being associated with relatively large areas of metal imbedded in a dielectric. Where metal areas are of limited area and relatively densely distributed across the face of the dielectric, erosion is another problem.
In practice it is not always possible to control wiring layouts to a sufficient extent as to ensure that the density of embedded metal is uniform across the entire chip area. In such situations, dishing and erosion are likely to occur in those areas where the density of embedded metal is relatively high. One way of dealing with this problem has been to introduce unconnected ‘dummy’ islands of metal into those parts of a given layer where the metal density would otherwise be low enough to cause dishing in the high density areas. In general, it has been found effective to add such islands wherever the areal density of metal is less than about 10 percent.
FIG. 1 shows a small portion of the upper surface of a partially completed integrated circuit 11. The areal density of metal in this part of the structure is low enough, relative to other parts, for dishing to be a potential problem so dummy islands 12 and 13, of width W, have been added, as discussed above. In this particular example, however, it is the case that a line of metallic wiring 14 was already present in a lower layer and that one of the dummy islands (13) happens to lie directly above it. Such a situation is undesirable, however, because of capacitive coupling between 13 and 14.
FIG. 2 is a cross-sectional view of FIG. 1 taken at plane 2-2. This shows multiple dielectric layers 23 as well as wiring line 14 and dummy islands 12 and 13. Also seen are two ground planes 22.
FIG. 3 illustrates the additional parasitic capacitance (normalized arbitrary units plotted as a function of the width of a signal line such as 14 in FIGS. 1 and 2) that can result when a dummy island such as 13 and/or 25 is included in the structure. Curve 31 is for the case where no dummy islands are present. Curve 32 is for the case where there is only a single dummy island (either 13 or 25, but not both) while curve 33 is the case where there are two dummy islands (13 and 25) involved, one above and one below the signal line. This data shows that an increase in parasitic capacitance of over 40% is possible in some cases, with an increase of about 20% being typical.
Thus, there is a need for a process that minimizes CMP dishing in areas of relatively high metal density without at the same time introducing excessive parasitic capacitance.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 5,798,298 (Yang et al.) shows a process to provide dummy lines to reduce dishing problems during CMP. In U.S. Pat. No. 5,924,066, Lur et al. show a dummy metal pattern with voids introduced into the dielectric between lines to lower the capacitance between adjoining lines (as opposed to superposed lines). U.S. Pat. No. 5,915,201(Chang et al.) take a similar approach to Lur et al. as just described. Kinugawa, in U.S. Pat. No. 5,929,528, teaches that dummy patterns and wiring must not overlap at all.